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quad, 12-bit, 50/65 msps, serial, lvds, 3 v a/d converter ad9229 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features four adcs in 1 package serial lvds digital output data rates to 780 mbps (ansi-644) data and frame clock outputs snr = 69.5 db (to nyquist) excellent linearity dnl = 0.3 lsb (typical) inl = 0.4 lsb (typical) 400 mhz full power analog bandwidth power dissipation 1,350 mw at 65 msps 985 mw at 50 msps 1 v p-p to 2 v p-p input voltage range 3.0 v supply operation power-down mode digital test pattern enable for timing alignments applications digital beam-forming systems for ultrasound wireless and wired broadband communications communication test equipment functional block diagram ad9229 12 12 12 12 vin+a vin?a d+a d?a sha pipeline adc serial lvds data rate multiplier ref select vin+b vin?b d+b d?b sha pipeline adc serial lvds vin+c vin?c d+c d?c sha pipeline adc serial lvds vin+d vin?d vref sense d+d d?d 0.5v fco+ fco? dco+ dco? sha pipeline adc serial lvds reft refb agnd clk lvdsbias pdwn dtp drvdd drgnd 04418-001 figure 1. general description the ad9229 is a quad, 12-bit, 65 msps analog-to-digital converter (adc) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. the product operates at up to a 65 msps conversion rate and is optimized for outstanding dynamic performance in applications where a small package size is critical. the adc requires a single 3 v power supply and ttl-/cmos- compatible sample rate clock for full performance operation. no external reference or driver components are required for many applications. the adc automatically multiplies the sample rate clock for the appropriate lvds serial data rate. a data clock (dco) for capturing data on the output and a frame clock (fco) trigger for signaling a new output byte are provided. power-down is supported and typically consumes 3 mw when enabled. fabricated with an advanced cmos process, the ad9229 is available in a pb-free, 48-lead lfcsp package. it is specified over the industrial temperature range of C40c to +85c. product highlights 1. four adcs are contained in a small, space-saving package. 2. a data clock out (dco) is provided, which operates up to 390 mhz and supports double-data rate operation (ddr). 3. the outputs of each adc are serialized lvds with data rates up to 780 mbps (12 bits 65 msps). 4. the ad9229 operates from a single 3.0 v power supply. 5. packaged in a pb-free, 48-lead lfcsp package. 6. the internal clock duty cycle stabilizer maintains performance over a wide range of input clock duty cycles.
ad9229 rev. a | page 2 of 40 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 ac specifications.......................................................................... 4 digital specifications ................................................................... 5 switching specifications .............................................................. 6 timing diagram ............................................................................... 7 absolute maximum ratings............................................................ 8 explanation of test levels ........................................................... 8 esd caution.................................................................................. 8 pin configuration and function descriptions............................. 9 equivalent circuits ......................................................................... 10 typical performance characteristics ........................................... 11 terminology .................................................................................... 16 theory of operation ...................................................................... 18 analog input considerations ................................................... 18 clock input considerations...................................................... 19 evaluation board ............................................................................ 24 power supplies ............................................................................ 24 input signals................................................................................ 24 output signals ............................................................................ 24 default operation and jumper selection settings................. 25 alternate analog input drive configuration......................... 25 outline dimensions ....................................................................... 39 ordering guide .......................................................................... 39 revision history 9/05rev. 0 to rev. a change to specifications.................................................................. 3 changes to differential input configurations section.............. 19 changes to exposed paddle thermal heat slug recommendations section........................................................ 23 changes to evaluation board section.......................................... 24 changes to table 11........................................................................ 36 3/05revision 0: initial version
ad9229 rev. a | page 3 of 40 specifications avdd = 3.0 v, drvdd = 3.0 v, maximum conversion rate, 2 v p-p differential input, 1.0 v internal reference, ain = C0.5 dbfs, un less otherwise noted. table 1. ad9229-50 ad9229-65 parameter temperature test level min typ max min typ max unit resolution 12 12 bits accuracy no missing codes full vi guaranteed guaranteed offset error full vi 5 25 5 25 mv offset matching full vi 5 25 5 25 mv gain error 1 full vi 0.3 2.5 0.3 2.5 % fs gain matching 1 full vi 0.2 1.5 0.2 1.5 % fs differential nonlinearity (dnl) 25c v 0.3 0.3 lsb full vi 0.3 0.6 0.3 0.7 lsb integral nonlinearity (inl) 25c v 0.6 0.4 lsb full vi 0.6 1 0.4 1 lsb temperature drift offset error full v 2 3 ppm/c gain error 1 full v 12 12 ppm/c reference voltage, vref = 1 v full v 16 16 ppm/c reference output voltage error, vref = 1 v full vi 10 30 10 30 mv load regulation @ 1.0 ma, vref = 1 v full v 3 3 mv output voltage error, vref = 0.5 v full vi 8 17 8 17 mv load regulation @ 0.5 ma, vref = 0.5 v full v 0.2 0.2 mv input resistance full v 7 7 k analog inputs differential input voltage range vref = 1 v full vi 2 2 v p-p differential input voltage range vref = 0.5 v full vi 1 1 v p-p common mode voltage full v 1.5 1.5 v input capacitance 2 full v 7 7 pf analog bandwidth, full power full v 400 400 mhz power supply avdd full iv 2.7 3.0 3.6 2.7 3.0 3.6 v drvdd full iv 2.7 3.0 3.6 2.7 3.0 3.6 v iavdd full vi 300 330 420 455 ma drvdd full vi 28 31 29 33 ma power dissipation 3 full vi 985 1083 1350 1465 mw power-down dissipation full v 3 3 mw crosstalk 4 full v C95 C95 db 1 gain error and gain temperature coefficients are based on the adc only, with a fixed 1.0 v external reference and a 2 v p-p di fferential analog input. 2 input capacitance refers to the effectiv e capacitance between one differential input pin and agnd. refer to figure 4 for the e quivalent analog input structure. 3 power dissipation measured with rated encode and 2.4 mhz analog input at C0.5 dbfs. 4 typical specification over the first nyquist zone.
ad9229 rev. a | page 4 of 40 ac specifications avdd = 3.0 v, drvdd = 3.0 v, maximum conversion rate, 2 v p-p differential input, 1.0 v internal reference, ain = C0.5 dbfs, un less otherwise noted. table 2. ad9229-50 ad9229-65 parameter temperature test level min typ max min typ max unit signal-to-noise ratio (snr) f in = 2.4 mhz full iv 69.5 70.4 69.0 70.2 db f in = 10.3 mhz 25c v 70.4 70.2 db f in = 25 mhz full vi 68.7 69.6 db f in = 30 mhz full vi 68.0 69.5 db f in = 70 mhz 25c v 67.2 67.1 db signal-to-noise ratio (sinad) f in = 2.4 mhz full v 70.0 69.8 db f in = 10.3 mhz 25c v 70.0 69.8 db f in = 25 mhz full vi 68.4 69.4 db f in = 30 mhz full vi 67.3 69.0 db f in = 70 mhz 25c v 66.8 66.7 db effective number of bits (enob) f in = 2.4 mhz full v 11.3 11.3 bits f in = 10.3 mhz 25c v 11.3 11.3 bits f in = 25 mhz full vi 11.1 11.2 bits f in = 30 mhz full vi 10.9 11.2 bits f in = 70 mhz 25c v 10.8 10.8 bits spurious-free dynamic range (sfdr) f in = 2.4 mhz full v 85 85 dbc f in = 10.3 mhz 25c v 85 85 dbc f in = 25 mhz full vi 76 85 dbc f in = 30 mhz full vi 73 85 dbc f in = 70 mhz 25c v 78 77 dbc worst harmonic f in = 2.4 mhz full v C85 C85 dbc (second or third) f in = 10.3 mhz 25c v C85 C85 dbc f in = 25 mhz full vi C85 C76 dbc f in = 30 mhz full vi C85 C73 dbc f in = 70 mhz 25c v C78 C77 dbc worst other f in = 2.4 mhz full v C90 C90 dbc (excluding second or third) f in = 10.3 mhz 25c v C90 C90 dbc f in = 25 mhz full vi C88 C81.7 dbc f in = 30 mhz full vi C88 C79.7 dbc f in = 70 mhz 25c v C85 C83 dbc two-tone intermodulation distortion (imd) f in1 = 15 mhz 25c v C73 C73 dbc ain1 and ain2 = C7.0 dbfs f in2 = 16 mhz f in1 = 69 mhz 25c v C68.5 C68.5 dbc f in2 = 70 mhz
ad9229 rev. a | page 5 of 40 digital specifications avdd = 3.0 v, drvdd = 3.0 v, maximum conversion rate, 2 v p-p differential input, 1.0 v internal reference, ain = C0.5 dbfs, un less otherwise noted. table 3. ad9229-50 ad9229-65 parameter temperature test level min typ max min typ max unit clock input logic compliance ttl/cmos ttl/cmos high level input voltage full iv 2.0 2.0 v low level input voltage full iv 0.8 0.8 v high level input current full vi 0.5 10 0.5 10 a low level input current full vi 0.5 10 0.5 10 a input capacitance 25c v 2 2 pf logic inputs (pdwn) logic 1 voltage full iv 2.0 2.0 v logic 0 voltage full iv 0.8 0.8 v high level input current full iv 0.5 10 0.5 10 a low level input current full iv 0.5 10 0.5 10 a input capacitance 25c v 2 2 pf digital outputs (d+, dC) logic compliance lvds lvds differential output voltage full vi 260 440 260 440 mv output offset voltage full vi 1.15 1.25 1.35 1.15 1.25 1.35 v output coding full vi offset binary offset binary
ad9229 rev. a | page 6 of 40 switching specifications avdd = 3.0 v, drvdd = 3.0 v, maximum conversion rate, 2 v p-p differential input, 1.0 v internal reference, ain = C0.5 dbfs, un less otherwise noted. table 4. ad9229-50 ad9229-65 parameter temp test level min typ max min typ max unit clock maximum clock rate full vi 50 65 msps minimum clock rate full iv 10 10 msps clock pulse width high (t eh ) full vi 8 10 6.2 7.7 ns clock pulse width low (t el ) full vi 8 10 6.2 7.7 ns output parameters propagation delay (t pd ) full vi 3.3 6.5 7.9 3.3 6.5 7.9 ns rise time (t r ) (20% to 80%) full v 250 250 ps fall time (t f ) (20% to 80%) full v 250 250 ps fco propagation delay (t fco ) full v 6.5 6.5 ns dco propagation delay (t cpd ) full v t fco + (t sample /24) t fco + (t sample /24) ns dco-to-data delay (t data ) full iv (t sample /24) C 250 (t sample /24) (t sample /24) + 250 (t sample /24) C 250 (t sample /24) (t sample /24) + 250 ps dco-to-fco delay (t frame ) full iv (t sample /24) C 250 (t sample /24) (t sample /24) + 250 (t sample /24) C 250 (t sample /24) (t sample /24) + 250 ps data-to-data skew (t data-max C t data-min ) full iv 100 250 100 250 ps wake-up time 25c v 4 4 ms pipeline latency full iv 10 10 clk cycles aperture aperture delay (t a ) 25c v 1.8 1.8 ns aperture uncertainty (jitter) 25c v <1 <1 ps rms out-of-range recovery time 25c v 2 2 clk cycles
ad9229 rev. a | page 7 of 40 timing diagram dco? dco+ d? d+ fco? fco+ ain clk n?1 n t eh t cpd t data msb (n ? 10) d10 (n ? 10) d9 (n ? 10) d8 (n ? 10) d7 (n ? 10) d6 (n ? 10) d5 (n ? 10) d4 (n ? 10) d3 (n ? 10) d2 (n ? 10) d1 (n ? 10) d0 (n ? 10) d10 (n ? 9) msb (n ? 9) t fco t pd t el t a 04418-002 t frame figure 2. timing diagram
ad9229 rev. a | page 8 of 40 absolute maximum ratings table 5. parameter with respect to rating electrical avdd agnd C0.3 v to +3.9 v drvdd drgnd C0.3 v to +3.9 v agnd drgnd C0.3 v to +0.3 v avdd drvdd C3.9 v to +3.9 v digital outputs (d+, dC, dco+, dcoC, fco+, fcoC) drgnd C0.3 v to drvdd lvdsbias drgnd C0.3 v to drvdd clk agnd C0.3 v to avdd vin+, vinC agnd C0.3 v to avdd pdwn, dtp agnd C0.3 v to avdd reft, refb agnd C0.3 v to avdd vref, sense agnd C0.3 v to avdd environmental operating temperature range (ambient) C40c to +85c maximum junction temperature 150c lead temperature (soldering, 10 sec) 300c storage temperature range (ambient) C65c to +150c thermal impedance 1 25c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. explanation of test levels i. 100% production tested. ii. 100% production tested at 25c and guaranteed by design and characterization at specified temperatures. iii. sample tested only. iv. parameter is guaranteed by design and characterization testing. v. parameter is a typical value only. vi. 100% production tested at 25c and guaranteed by design and characterization for industrial temperature range. 1 ja for a 4-layer pcb with a solid ground plane in still air. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad9229 rev. a | page 9 of 40 pin configuration and fu nction descriptions 13 14 15 16 17 18 19 20 21 22 23 24 vin?b vin+b agnd avdd sense vref refb reft avdd agnd vin+c vin?c 48 47 46 45 44 43 42 41 40 39 38 37 dco+ dco? fco+ fco? d+a d?a d+b d?b d+c d?c d+d d?d 1 2 3 4 5 6 7 8 9 10 11 12 drgnd drvdd nc dtp avdd agnd pdwn avdd agnd vin+a vin?a agnd drvdd lvdsbias agnd avdd agnd clk avdd agnd vin+d vin?d agnd 35 drgnd 36 34 33 32 31 30 29 28 27 26 25 ad9229 top view (not to scale) pin 1 indicator exposed paddle, pin 0 (bottom of package) 04418-003 nc = no connect figure 3. lfcsp top view table 6. pin function descriptions pin no. mnemonic description 5, 8, 16, 21, 29, 32 avdd analog supply 6, 9, 12, 15, 22, 25, 28, 31, 33 agnd analog ground 2, 35 drvdd digital output supply 1, 36 drgnd digital ground 0 agnd exposed paddle/thermal heat slug (located on bottom of package) 3 nc no connect 4 dtp digital test pattern enable 7 pdwn power-down selection (avdd = power down) 10 vin+a adc a analog inputtrue 11 vinCa adc a analog input complement 13 vinCb adc b analog input complement 14 vin+b adc b analog inputtrue 17 sense reference mode selection 18 vref voltage reference input/output 19 refb differential reference (bottom) 20 reft differential reference (top) 23 vin+c adc c analog inputtrue 24 vinCc adc c analog input complement pin no. mnemonic description 26 vinCd adc d analog input complement 27 vin+d adc d analog inputtrue 30 clk input clock 34 lvdsbias lvds output current set resistor pin 37 dCd adc d complement digital output 38 d+d adc d true digital output 39 dCc adc c complement digital output 40 d+c adc c true digital output 41 dCb adc b complement digital output 42 d+b adc b true digital output 43 dCa adc a complement digital output 44 d+a adc a true digital output 45 fcoC frame clock indicator complement output 46 fco+ frame clock indicatortrue output 47 dcoC data clock output complement 48 dco+ data clock outputtrue
ad9229 rev. a | page 10 of 40 equivalent circuits avdd agnd vin+, vin? 04418-004 figure 4. equivalent analog input circuit avdd 170 agnd c l k 04418-005 figure 5. equivalent clock input circuit avdd 375 agnd pdwn 04418-006 figure 6. equivalent digital input circuit drvdd drgnd d? d+ v v 04418-007 v v figure 7. equivalent digital output circuit avdd 375 100k agnd dtp 04418-051 figure 8. equivalent dtp input circuit
ad9229 rev. a | page 11 of 40 typical performance characteristics frequency (mhz) amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?120 ?100 0 8.1 4.1 12.2 16.3 20.3 24.4 28.4 32.5 04418-009 ain = ?0.5dbfs snr = 70.4db enob = 11.4 bits sfdr = 85.8dbc figure 9. single-tone 32k fft with f in = 2.4 mhz, f sample = 65 msps frequency (mhz) amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?120 ?100 0 8.1 4.1 12.2 16.3 20.3 24.4 28.4 32.5 04418-010 ain = ?0.5dbfs snr = 69.6db enob = 11.3 bits sfdr = 82.4dbc figure 10. single-tone 32k fft with f in = 30 mhz, f sample = 65 msps frequency (mhz) amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?120 ?100 0 8.1 4.1 12.2 16.3 20.3 24.4 28.4 32.5 04418-011 ain = ?0.5dbfs snr = 68.5db enob = 11.1 bits sfdr = 81.3dbc figure 11. single-tone 32k fft with f in = 70 mhz, f sample = 65 msps frequency (mhz) amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?120 ?100 0 8.1 4.1 12.2 16.3 20.3 24.4 28.4 32.5 04418-012 ain = ?0.5dbfs snr = 68.1db enob = 11.0 bits sfdr = 77.0dbc figure 12. single-tone 32k fft with f in = 120 mhz, f sample = 65 msps encode (msps) snr/sfdr (db) 90 85 80 75 70 60 65 10 20 15 25 30 35 40 45 50 04418-013 2v p-p, snr (db) 1v p-p, sfdr (dbc) 1v p-p, snr (db) 2v p-p, sfdr (dbc) ain = ?0.5dbfs figure 13. snr/sfdr vs. f sample , f in = 10.3 mhz, f sample = 50 msps encode (msps) snr/sfdr (db) 90 85 80 75 70 60 65 10 20 15 25 30 35 40 45 50 04418-014 2v p-p, snr (db) 1v p-p, sfdr (dbc) 1v p-p, snr (db) 2v p-p, sfdr (dbc) ain = ?0.5dbfs figure 14. snr/sfdr vs. f sample , f in = 25 mhz, f sample = 50 msps
ad9229 rev. a | page 12 of 40 encode (msps) snr/sfdr (db) 95 90 85 80 75 70 60 65 10 20 15 25 30 35 40 45 65 50 55 60 04418-015 2v p-p, snr (db) 1v p-p, sfdr (dbc) 1v p-p, snr (db) 2v p-p, sfdr (dbc) ain = ?0.5dbfs figure 15. snr/sfdr vs. f sample , f in = 10.3 mhz, f sample = 65 msps encode (msps) snr/sfdr (db) 85 80 75 70 60 65 10 20 15 25 30 35 40 45 65 50 55 60 04418-016 2v p-p, snr (db) 1v p-p, sfdr (dbc) 1v p-p, snr (db) 2v p-p, sfdr (dbc) ain = ?0.5dbfs figure 16. snr/sfdr vs. f sample , f in = 30 mhz, f sample = 65 msps analog input level (dbfs) snr/sfdr (db) 90 80 70 60 40 30 50 10 0 20 ?60 ?10 ?20 ?30 ?40 ?50 0 04418-017 80 db reference 1v p-p, sfdr (dbc) 1v p-p, snr (db) 2v p-p, sfdr (dbc) 2v p-p, snr (db) figure 17. snr/sfdr vs. analog input level, f in = 10.3 mhz, f sample = 50 msps analog input level (dbfs) snr/sfdr (db) 90 80 70 60 40 30 50 10 0 20 ?60 ?10 ?20 ?30 ?40 ?50 0 04418-018 80 db reference 1v p-p, sfdr (dbc) 1v p-p, snr (db) 2v p-p, sfdr (dbc) 2v p-p, snr (db) figure 18. snr/sfdr vs. analog input level, f in =25 mhz, f sample = 50 msps analog input level (dbfs) snr/sfdr (db) 90 80 70 60 40 30 50 10 0 20 ?60 ?10 ?20 ?30 ?40 ?50 0 04418-019 80 db reference 1v p-p, sfdr (dbc) 1v p-p, snr (db) 2v p-p, sfdr (dbc) 2v p-p, snr (db) figure 19. snr/sfdr vs. analog input level, f in = 10.3 mhz, f sample = 65 msps analog input level (dbfs) snr/sfdr (db) 90 80 70 60 40 30 50 10 0 20 ?60 ?10 ?20 ?30 ?40 ?50 0 04418-020 80 db reference 1v p-p, sfdr (dbc) 1v p-p, snr (db) 2v p-p, sfdr (dbc) 2v p-p, snr (db) figure 20. snr/sfdr vs. analog input level, f in = 30 mhz, f sample = 65 msps
ad9229 rev. a | page 13 of 40 frequency (mhz) snr/sfdr (db) 90 85 80 75 65 60 70 50 45 55 1 100 10 1000 04418-021 sfdr (dbc) snr (db) figure 21. snr/sfdr vs. f in , f sample = 65 mhz frequency (mhz) amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?120 ?100 0 8.1 4.1 12.2 16.3 20.3 24.4 28.4 32.5 04418-022 ain1 and ain2= ?7.0dbfs sfdr = 73.0dbc imd2 = 80.5dbc imd3 = 73.0dbc figure 22. two-tone 32k fft with f in1 = 15 mhz and f in2 = 16 mhz, f sample = 65 msps frequency (mhz) amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?120 ?100 0 8.1 4.1 12.2 16.3 20.3 24.4 28.4 32.5 04418-023 ain1 and ain2= ?7.0dbfs sfdr = 68.5dbc imd2 = 77.0dbc imd3 = 68.5dbc figure 23. two-tone 32k fft with f in1 = 69 mhz and f in2 = 70 mhz, f sample = 65 msps analog input level (dbfs) sfdr (db) 80 70 60 40 30 50 10 0 20 ?60 ?19 ?10 ?28 ?36 ?44 ?52 ?56 ?15 ?23 ?32 ?40 ?48 ?7 04418-024 80 db reference 2v p-p, sfdr (dbc) 1v p-p, sfdr (dbc) figure 24. two-tone sfdr vs. analog input level, f in1 = 15 mhz and f in2 = 16 mhz, f sample = 65 msps analog input level (dbfs) sfdr (db) 80 70 60 40 30 50 10 0 20 ?60 ?19 ?10 ?28 ?36 ?44 ?52 ?56 ?15 ?23 ?32 ?40 ?48 ?7 04418-025 80 db reference 2v p-p, sfdr (dbc) 1v p-p, sfdr (dbc) figure 25. two-tone sfdr vs. analog input level, f in1 = 69 mhz and f in2 = 70 mhz, f sample = 65 msps temperature ( c) snr/sfdr (db) 90 85 75 80 65 60 70 ?40 60 80 40 20 0 ?20 04418-026 2v p-p, sfdr (dbc) 2v p-p, sinad (db) 1v p-p, sinad (db) 1v p-p, sfdr (dbc) figure 26. sinad/sfdr vs. temperature, f in 10.3 mhz, f sample = 65 msps
ad9229 rev. a | page 14 of 40 temperature ( c) gain error (ppm/ c) 15 10 0 5 ?10 ?15 ?20 ?5 ?40 60 80 40 20 0 ?20 04418-027 figure 27. gain error vs. temperature code inl (lsb) 0.5 0 0.1 0.2 0.3 0.4 ?0.1 ?0.2 ?0.3 ?0.5 ?0.4 0 1024 512 1536 2048 2560 3072 3584 4095 04418-028 figure 28. typical inl, f in = 2.4 mhz, f sample = 65 msps code dnl (lsb) 0.5 0 0.1 0.2 0.3 0.4 ?0.1 ?0.2 ?0.3 ?0.5 ?0.4 0 1024 512 1536 2048 2560 3072 3584 4095 04418-030 figure 29. typical dnl, f in = 2.4 mhz, f sample = 65 msps frequency (mhz) cmrr (db) ?40 ?60 ?50 ?70 ?80 02530 20 15 10 5 04418-031 figure 30. cmrr vs. frequency, f sample = 65 msps code number of hits (1m) 10 9 8 7 6 4 5 0 3 2 1 n? 2 n ? 3 n ? 1 n n + 1 n + 2 n + 3 04418-039 0.36lsb rms figure 31. input referred noise histogram, f sample = 65 msps frequency (mhz) amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?120 ?100 0 8.1 4.1 12.2 16.3 20.3 24.4 28.4 32.5 04418-035 npr = 60.8db notch = 18mhz notch width = 3mhz figure 32. noise power ratio (npr), f sample = 65 msps
ad9229 rev. a | page 15 of 40 frequency (mhz) fundamental level (db) 0 ?6 ?5 ?7 ?8 ?2 ?1 ?3 ?4 0 450 500 400 350 300 250 200 150 100 50 04418-038 figure 33. full power bandwidth vs. frequency, f sample = 65 msps
ad9229 rev. a | page 16 of 40 terminology analog bandwidth analog bandwidth is the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db from full scale. aperture delay aperture delay is a measure of the sample-and-hold amplifier (sha) performance and is measured from the 50% point rising edge of the clock input to the time at which the input signal is held for conversion. aperture uncertainty (jitter) aperture jitter is the variation in aperture delay for successive samples and can be manifested as frequency-dependent noise on the adc input. clock pulse width and duty cycle pulse width high is the minimum amount of time that the clock pulse should be left in the logic 1 state to achieve rated performance. pulse width low is the minimum time the clock pulse should be left in the low state. at a given clock rate, these specifications define an acceptable clock duty cycle. common mode rejection ratio (cmrr) cmrr is defined as the amount of rejection on the differential analog inputs when a common signal is applied. typically expressed as 20 log (differential gain/common-mode gain). crosstalk crosstalk is defined as the measure of any feedthrough coupling onto the quiet channel when all other channels are driven by a full-scale signal. differential analog input voltage range the peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. peak differential voltage is computed by observing the voltage on a pin and subtracting the voltage from a second pin that is 180 out of phase. differential nonlinearity (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to an n-bit resolution indicates that all 2 n codes, respectively, must be present over all operating ranges. effective number of bits (enob) for a sine wave, sinad can be expressed in terms of the number of bits. using the following formula, it is possible to obtain a measure of performance expressed as n, the effective number of bits: n = (sinad C 1.76)/6.02 full power bandwidth full power bandwidth is the measured C3 db point at the analog front-end input relative to the frequency measured. gain error the largest gain error is specified and is considered the difference between the measured and ideal full-scale input voltage range. gain matching expressed as a percentage of fsr and computed using the following equation: % 100 2 min max min max ? ? ? ? ? ? + ? = fsr fsr fsr fsr matching gain where fsr max is the most positive gain error of the adcs, and fsr min is the most negative gain error of the adcs. input-referred noise input-referred noise is a measure of the wideband noise generated by the adc core. histograms of the output codes are created while a dc signal is applied to the adc input. input- referred noise is calculated using the standard deviation of the histograms and presented in terms of lsb rms. integral nonlinearity (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 0.5 lsb before the first code transition. positive full scale is defined as a level 1.5 lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. noise power ratio (npr) npr is the full-scale rms noise power injected into the adc vs. the rejected band of interest (notch depth measured). offset error the largest offset error is specified and is considered the difference between the measured and ideal voltage at the analog input that produces the midscale code at the outputs. offset matching expressed in millivolts and computed using the following equation: offset matching = off max ? off min where off max is the most positive offset error, and off min is the most negative offset error.
ad9229 rev. a | page 17 of 40 out-of-range recovery time out-of-range recovery time is the time it takes for the adc to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. output propagation delay the delay between the clock logic threshold and the time when all bits are within valid logic levels. second and third harmonic distortion the ratio of the rms signal amplitude to the rms value of the second or third harmonic component, reported in decibels relative to the carrier. signal-to noise and distortion (sinad) ratio sinad is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. spurious-free dynamic range (sfdr) sfdr is the difference in decibels between the rms amplitude of the input signal and the peak spurious signal. temp er atu re d r i f t the temperature drift for offset error and gain error specifies the maximum change from the initial (25c) value to the value at t min or t max . two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. it may be reported in decibels relative to the carrier (that is, degrades as signal levels are lowered) or in decibels relative to full scale (always related back to converter full scale).
ad9229 rev. a | page 18 of 40 theory of operation the ad9229 architecture consists of a front-end switched capa- citor sample-and-hold amplifier (sha) followed by a pipelined adc. the pipelined adc is divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. each stage provides sufficient overlap to correct for flash errors in the preceding stages. the quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched capacitor dac and interstage residue amplifier (mdac). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the input stage contains a differential sha that can be config- ured as ac- or dc-coupled in differential or single-ended modes. the output staging block aligns the data, carries out the error correction, and passes the data to the output buffers. the data is then serialized and aligned to the frame and output clock. analog input considerations the analog input to the ad9229 is a differential switched- capacitor sha that has been designed for optimum perfor- mance while processing a differential input signal. the sha input can support a wide common-mode range and maintain excellent performance. an input common-mode voltage of midsupply minimizes signal-dependent errors and provides optimum performance. 04418-029 h h vin+ vin? c par c par s s s s figure 34. switched-c apacitor sha input the clock signal alternately switches the sha between sample mode and hold mode (see figure 34). when the sha is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. this passive network creates a low-pass filter at the adcs input; therefore, the precise values are dependent on the application. the analog inputs of the ad9229 are not internally dc-biased. in ac-coupled applications, the user must provide this bias externally. for optimum performance, set the device so that v cm = av d d /2; however, the device can function over a wider range with reasonable performance (see figure 35 and figure 36). analog input common-mode voltage (v) snr/sfdr (db) 90 85 75 80 65 60 70 0 2.5 3.0 2.0 1.5 1.0 0.5 04418-053 2v p-p, sfdr (dbc) 2v p-p, snr (db) 1v p-p, snr (db) 1v p-p, sfdr (dbc) figure 35. snr/sfdr vs. common-mode voltage, f in = 2.4 mhz, f sample = 65 msps analog input common-mode voltage (v) snr/sfdr (db) 90 65 55 60 45 40 50 85 75 80 70 0 2.5 3.0 2.0 1.5 1.0 0.5 04418-054 2v p-p, sfdr (dbc) 2v p-p, snr (db) 1v p-p, snr (db) 1v p-p, sfdr (dbc) figure 36. snr/sfdr vs. common-mode voltage, f in = 30 mhz, f sample = 65 msps for best dynamic performance, the source impedances driving vin+ and vin? should be matched such that common-mode settling errors are symmetrical. these errors are reduced by the common-mode rejection of the adc.
ad9229 rev. a | page 19 of 40 an internal reference buffer creates the positive and negative reference voltages, reft and refb, respectively, that defines the span of the adc core. the output common-mode of the reference buffer is set to midsupply, and the reft and refb voltages and span are defined as reft = 1/2 ( av d d + vref ) refb = 1/2 ( av d d ? vref ) span = 2 ( reft ? refb ) = 2 vref it can be seen from the equations above that the reft and refb voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the vref voltage. the internal voltage reference can be pin-strapped to fixed values of 0.5 v or 1.0 v or adjusted within the same range, as discussed in the internal reference connection section. maximum snr performance is achieved by setting the ad9229 to the largest input span of 2 v p-p. the sha should be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. the minimum and maximum common-mode input levels are defined in figure 35 and figure 36. differential input configurations optimum performance is achieved by driving the ad9229 in a differential input configuration. for ultrasound applications, the ad8332 differential driver provides excellent performance and a flexible interface to the adc (see figure 37). ad8332 1.0k 1.0k 374 187 04418-032 ad9229 vin+ vin? avdd agnd r r c 0.1 f 187nh vref 0.1 f 0.1 f 0.1 f 0.1 f10 f 0.1 f 1v p-p 0.1 f avdd lna 120nh vga voh vip inh 22p lmd vin lop lon vol 18nf 274 however, the noise performance of most amplifiers is not adequate to achieve the true performance of the ad9229. for applications where snr is a key parameter, differential transfor- mer coupling is the recommended input configuration. an example of this is shown in figure 38. in any configuration, the value of the shunt capacitor, c, is dependent on the input frequency and may need to be reduced or removed. 04418-033 ad9229 vin+ vin? avdd agnd 2 vp-p r r c 49.9 0.1 f 1k 1k avdd figure 38. differential transformer?coupled configuration single-ended input configuration a single-ended input can provide adequate performance in cost-sensitive applications. in this configuration, sfdr and distortion performance degrade due to the large input common-mode swing. however, if the source impedances on each input are matched, there should be little effect on snr performance. figure 39 details a typical single-ended input configuration. 04418-034 2v p-p r r c 49.9 0.1 f 10 f 10 f 0.1 f ad9229 vin+ vin? avdd agnd avdd 1k 1k 1k 1k typical high speed adcs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensi- tive to clock duty cycle. typically, a 10% tolerance is required on the clock duty cycle to maintain dynamic performance charac- teristics. the ad9229 has a self-contained clock duty cycle stabilizer that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the performance of the ad9229. an on-board phase-locked loop (pll) multiplies the input clock rate for the purpose of shifting the serial data out. the stability criteria for the pll limits the minimum sample clock rate of the adc to 10 msps. assuming steady state operation of the input clock, any sudden change in the sampling rate could create an out-of-lock condition leading to invalid outputs at the dco, fco, and data out pins.
ad9229 rev. a | page 20 of 40 high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given full-scale input frequency (f a ) due only to aperture jitter (t a ) can be calculated with the following equation: snr degradation = 20 log 10 [1/2 f a t a ] in the equation, the rms aperture jitter, t a , represents the root sum square of all jitter sources, which include the clock input, analog input signal, and adc aperture jitter specification. applications that require undersampling are particularly sensitive to jitter. the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9229. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal-controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. power dissipation and power-down mode as shown in figure 40 and figure 41, the power dissipated by the ad9229 is proportional to its sample rate. the digital power dissipation does not vary much because it is determined primarily by the drvdd supply and bias current of the lvds output drivers. encode (msps) power (mw) 1200 900 800 600 700 1000 1100 current (ma) 350 250 0 100 50 200 150 300 10 50 40 45 30 35 20 25 15 04418-056 i avdd total power i drvdd figure 40. supply current vs. f sample for f in = 10.3 mhz, f sample = 50 msps encode (msps) power (mw) 1400 1100 1000 800 900 1200 1300 current (ma) 500 300 250 200 0 50 150 100 350 400 450 10 50 60 40 30 20 04418-055 i avdd total power i drvdd figure 41. supply current vs. f sample for f in = 10.3 mhz, f sample = 65 msps by asserting the pdwn pin high, the ad9229 is placed in power-down mode. in this state, the adc typically dissipates 3 mw. during power-down, the lvds output drivers are placed in a high impedance state. reasserting the pdwn pin low returns the ad9229 to normal operating mode. in power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, pll, and biasing networks. the decoupling capacitors on reft and refb are discharged when entering standby mode and then must be recharged when returning to normal operation. as a result, the wake-up time is related to the time spent in the power-down mode; shorter cycles result in proportionally shorter wake-up times. with the recommended 0.1 f and 10 f decoupling capacitors on reft and refb, it takes approximately 1 sec to fully discharge the reference buffer decoupling capacitors and 4 ms to restore full operation. digital outputs the ad9229s differential outputs conform to the ansi-644 lvds standard. to set the lvds bias current, place a resistor (rset is nominally equal to 4.0 k) to ground at the lvdsbias pin. the rset resistor current is derived on-chip and sets the output current at each output equal to a nominal 3.5 ma. a 100 differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing at the receiver. to adjust the differential signal swing, simply change the resistor to a different value, as shown in table 7. table 7. lvdsbias pin configuration rset differential output swing 3.7 k 375 mv p-p 4.0 k (default) 350 mv p-p 4.3 k 325 mv p-p
ad9229 rev. a | page 21 of 40 the ad9229s lvds outputs facilitate interfacing with lvds receivers in custom asics and fpgas that have lvds capa- bility for superior switching performance in noisy environ- ments. single point-to-point net topologies are recommended with a 100 termination resistor placed as close to the receiver as possible. it is recommended to keep the trace length no longer than 12 inches and to keep differential output traces close together and at equal lengths. the format of the output data is offset binary. an example of the output coding format can be found in table 8. table 8. digital output coding code (vin+) ? (vin?), input span = 2 v p-p (v) (vin+) ? (vin?), input span = 1 v p-p (v) digital output offset binary (d11 ... d0) 4095 1.000 0.500 1111 1111 1111 2048 0 0 1000 0000 0000 2047 ?0.000488 ?0.000244 0111 1111 1111 0 ?1.00 ?0.5000 0000 0000 0000 timing data from each adc is serialized and provided on a separate channel. the data rate for each serial stream is equal to 12 bits times the sample clock rate, with a maximum of 780 bps (12 bits 65 msps = 780 bps). the lowest typical conversion rate is 10 msps. two output clocks are provided to assist in capturing data from the ad9229. the dco is used to clock the output data and is equal to six times the sampling clock (clk) rate. data is clocked out of the ad9229 and can be captured on the rising and falling edges of the dco that supports double-data rate (ddr) capturing. the frame clock out (fco) is used to signal the start of a new output byte and is equal to the sampling clock rate. see the timing diagram shown in figure 2 for more information. dtp pin the digital test pattern (dtp) pin can be enabled for two types of test patterns, as summarized in table 9. when the dtp is tied to avdd/3, all the adc channel outputs shift out the following pattern: 1000 0000 0000. when the dtp is tied to 2 avdd/3, all the adc channel outputs shift out the following pattern: 1010 1010 1010. the fco and dco outputs still work as usual while all channels shift out the test pattern. this pattern allows the user to perform timing alignment adjustments between the fco, dco, and the output data. for normal operation, this pin should be tied to agnd. table 9. digital test pattern pin settings selected dtp dtp voltage resulting d+ and dC resulting fco and dco normal operation agnd normal operation normal operation dtp1 avdd/3 1000 0000 0000 normal operation dtp2 2 avdd/3 1010 1010 1010 normal operation restricted avdd n/a n/a voltage reference a stable and accurate 0.5 v voltage reference is built into the ad9229. the input range can be adjusted by varying the refer- ence voltage applied to the ad9229, using either the internal reference or an externally applied reference voltage. the input span of the adc tracks reference voltage changes linearly. when applying the decoupling capacitors to the vref, reft, and refb pins, use ceramic, low esr capacitors. these capacitors should be close to the adc pins and on the same layer of the pcb as the ad9229. the recommended capacitor values and configurations for the ad9229 reference pin can be found in figure 42 and figure 43. table 10. reference settings selected mode sense voltage resulting vref (v) resulting differential span (v p-p) external reference avdd n/a 2 external reference internal, 1 v p-p fsr vref 0.5 1.0 programmable 0.2 v to vref 0.5 (1 + r2/r1) 2 vref internal, 2 v p-p fsr agnd to 0.2 v 1.0 2.0 internal reference connection a comparator within the ad9229 detects the potential at the sense pin and configures the reference into four possible states (summarized in table 10). if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 42), setting vref to 1 v. connecting the sense pin to the vref pin switches the amplifier output to the sense pin, configuring the internal op amp circuit as a voltage follower and providing a 0.5 v reference output. if an external resistor divider is connected as shown in figure 43, the switch is again set to the sense pin. this puts the reference amplifier in a noninverting mode and defines the vref output as ? ? ? ? ? ? + = 1 5 . 0 in all reference configurations, reft and refb establish their input span of the adc core. the analog input full-scale range of the adc equals twice the voltage at the reference pin for either an internal or an external reference configuration.
ad9229 rev. a | page 22 of 40 10 f 0.1 f vref sense 0.5v reft 0.1 f 0.1 f 10 f 0.1 f refb select logic adc core + 04418-036 vin? vin+ figure 42. internal reference configuration 10 f 0.1 f vref 0.5v reft 0.1 f 0.1 f 10 f 0.1 f refb select logic adc core + + 04418-037 vin? vin+ sense r2 r1 figure 43. programmable reference configuration if the internal reference of the ad9229 is used to drive multiple converters to improve gain matching, the loading of the refer- ence by the other converters must be considered. figure 44 depicts how the internal reference voltage is affected by loading. i load (ma) vref error (%) 0.05 ?0.20 ?0.15 ?0.30 ?0.35 ?0.25 ?0.05 0 ?0.10 0 1.8 2.0 1.6 1.2 1.4 1.0 0.8 0.6 0.4 0.2 04418-058 vref = 0.5v vref = 1.0v figure 44. vref accuracy vs. load external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or improve thermal drift charac- teristics. figure 45 shows the typical drift characteristics of the internal reference. temperature ( c) vref error (%) 0.10 0 ?0.04 ?0.02 ?0.08 ?0.10 ?0.06 0.08 0.04 0.06 0.02 ?40 65 80 50 35 20 5 ?10 ?25 04418-057 vref = 0.5v vref = 1.0v figure 45. typical vref drift when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. the external reference is loaded with an equivalent 7 k load. an internal reference buffer generates the positive and negative full-scale references, reft and refb, for the adc core. therefore, the external reference must be limited to a maximum of 1 v. power and ground recommendations when connecting power to the ad9229, it is recommended that two separate 3.0 v supplies be used: one for analog (avdd) and one for digital (drvdd). if only one supply is available, it should be routed to the avdd first and tapped off and isolated with a ferrite bead or filter choke with decoupling capacitors proceeding. the user can employ several different decoupling capacitors to cover both high and low frequencies. these should be located close to the point of entry at the pc board level and close to the parts with minimal trace length. a single pc board ground plane should be sufficient when using the ad9229. with proper decoupling and smart parti- tioning of the pc boards analog, digital, and clock sections, optimum performance is easily achieved.
ad9229 rev. a | page 23 of 40 exposed paddle thermal heat slug recommendations it is mandatory that the exposed paddle on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance of the ad9229. a continuous exposed copper plane on the pcb should mate to the ad9229 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be solder or epoxy filled (plugged). to maximize the solder coverage and adhesion between the adc and pcb, overlay a silkscreen to partition the continuous copper plane on the pcb into several uniform sections. this provides several tie points between the two during the reflow process. using one continuous plane with no silkscreen partitions only guarantees one tie point between the adc and pcb. see figure 46 for a pcb layout example. for detailed information on packaging and the pcb layout of chip scale packages, visit www.analog.com. silkscreen partition pin 1 indicator 04418-052 figure 46. typical pcb layout
ad9229 rev. a | page 24 of 40 evaluation board the ad9229 evaluation board provides all of the support cir- cuitry required to operate the adc in its various modes and configurations. the converter can be driven differentially through a transformer (default) or through the ad8332 driver. the adc can also be driven in a single-ended fashion. separate power pins are provided to isolate the dut from the ad8332 drive circuitry. each input configuration can be selected by proper connection of various jumpers (see figure 48 to figure 52). figure 47 shows the typical bench characterization setup used to evaluate the ac performance of the ad9229. it is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the ultimate performance of the converter. proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. see figure 47 to figure 57 for complete schematics and layout plots that demonstrate the routing and grounding techniques that should be applied at the system level. power supplies this evaluation board comes with a wall mountable switching power supply that provides a 6 v, 2 a maximum output. simply connect the supply to the rated 100 v to 240 v ac wall outlet at 47 hz to 63 hz. the other end is a 2.1 mm inner diameter jack that connects to the pcb at p503. once on the pc board, the 6 v supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias to each of the various sections on the board. when operating the evaluation board in a nondefault condition, l504 to l506 can be removed to disconnect the switching power supply. this enables the user to individually bias each section of the board. use p501 to connect a different supply for each section. at least one 3.0 v supply is needed with a 1 a current capability for avdd_dut and drvdd_dut; however, it is recommended that separate supplies be used for both analog and digital. to operate the evaluation board using the vga option, a separate 5.0 v analog supply is needed in addition to the other 3.0 v supplies. the 5.0 v supply, or avdd_vga, should have a 1 a current capability as well. input signals when connecting the clock and analog source, use clean signal generators with low phase noise, such as rohde & schwarz smhu or hp8644 signal generators or the equivalent. use 1 m long, shielded, rg-58, 50 coaxial cable for making connections to the evaluation board. dial in the desired frequency and amplitude within the adcs specifications tables. typically, most adi evaluation boards can accept a ~2.8 v p-p or 13 dbm sine wave input for the clock. when connecting the analog input source, it is recommended to use a multipole, narrow-band band-pass filter with 50 terminations. adi uses tte, allen avionics, and k&l types of band-pass filters. the filter should be connected directly to the evaluation board if possible. output signals the default setup uses the hsc-adc-fpga high speed deserialization board, which deserializes the digital output data and converts it to parallel cmos. these two channels interface directly with adis standard dual-channel fifo data capture board (hsc-adc-evala-dc). two of the four channels can then be evaluated at the same time. for more information on channel settings on these boards and their optional settings, visit www.analog.com/fifo. rohde & schwarz, smhu, 2v p-p signal synthesizer rohde & schwarz, smhu, 2v p-p signal synthesizer band-pass filter xfmr input clk cha?chd 12-bit serial lvds 2 ch 12-bit parallel cmos usb connection ad9229 evaluation board hsc-adc-fpga high speed deserialization board 04418-040 hsc-adc-evala-dc fifo data capture board pc running adc analyzer 3.0v ?+ ?+ avdd_dut drvdd_dut gnd gnd ?+ 5.0v gnd avdd_vga 3.0v 6v dc 2amax wall outlet 100v to 240v ac 47hz to 63hz switching power supply figure 47. evaluation board connections
ad9229 rev. a | page 25 of 40 default operation and jumper selection settings the following is a list of the default and optional settings or modes allowed on the ad9229 rev c evaluation board. ? power: connect the switching power supply that is supplied in the evaluation kit between a rated 100 v to 240 v ac wall outlet at 47 hz to 63 hz and p503. ? ain: the evaluation board is set up for a transformer coupled analog input with optimum 50 impedance matching out to 400 mhz. for more bandwidth response, the 2.2 pf differential capacitor across the analog inputs could be changed or removed. the common mode of the analog inputs is developed from the center tap of the transformer or avdd_dut/2. ? vref: vref is set to 1.0 v by tying the sense pin to ground, r224. this causes the adc to operate in 2.0 v p-p full-scale range. a number of other vref options are available on the evaluation board, including 1.0 v p-p full- scale range, a variable range that the user can set by choosing r219 and r220 as well as a separate external reference option using the adr510 or adr520. simply populate r218 and r222 and remove c208. to use these optional vref modes, switch the jumper setting on r221 to r224. proper use of the vref options is noted in the voltage reference section. ? clock: the clock input circuitry is derived from a simple logic circuit using a high speed inverter that adds a very low amount of jitter to the clock path. the clock input is 50 terminated and ac-coupled to handle sine wave type inputs. if using an oscillator, two oscillator footprint options are also available (osc200-201) to check the adcs performance. j203 and j204 give the user flexibility in using the enable pin, which is common on most oscillators. ? pwdn: to enable the power-down feature, simply short jp201 to avdd on the pwdn pin. ? dtp: to enable one of the two digital test patterns on digital outputs of the adc, use jp202. if pins 2 and 3 on jp202 are tied together (1.0 v source), this enables test pattern 1000 0000 0000. if pins 1 and 2 on jp202 are tied together (2.0 v source), this enables test pattern 1010 1010 1010. see the dtp pin section for more details. ? lvdsbias: to change the level of the lvds output level swing, simply change the value of r204. other recom- mended values can be found in the digital outputs section. ? d+, dC: if an alternate data capture method to the setup described in figure 47 is used, optional receiver terminations, r205 to r210, can be installed next to the high speed backplane connector. alternate analog input drive configuration the following is a brief description of the alternate analog input drive configuration using the ad8332 dual vga. this parti- cular drive option may need to be populated, in which case all the necessary components are listed in table 11. this table lists the necessary settings to properly configure the evaluation board for this option. for more details on the ad8332 dual vga, how it works, and its optional pin settings, consult the ad8332 data sheet. to configure the analog input to drive the vga instead of the default transformer option, the following components need to be removed and/or changed. 1. remove r102, r115, r128, r141, t101, t102, t103, and t1044 in the default analog input path. 2. populate r101, r114, r127, and r140 with 0 resistors in the analog input path. 3. populate r106, r107, r119, r120, r132, r133, r144, and r145 with 10 k resistors to provide an input common- mode level to the analog input. 4. populate r105, r113, r118, r124, r131, r137, r151, and r43 with 0 resistors in the analog input path. 5. currently l305 to l312 and l405 to l412 are populated with 0 resistors to allow signal connection. this area allows the user to design a filter if additional requirements are necessary.
ad9229 rev. a | page 26 of 40 vin_c vin_c r154 dnp r134 33 fb108 10 fb109 10 r136 33 r130 0 r129 0 fb107 10 r135 1k r162 499 r132 1k dnp r133 1k dnp r137 0 dnp c118 2.2pf r158 dnp c117 dnp cm3 cm3 1 2 34 5 6 ch_c ch_c c115 0.1 f c116 0.1 f a in p106 dnp r127 0 dnp r128 65 a in p105 channel c inh3 vga input connection t103 c121 0.1 f r139 1k r138 1k c120 dnp cm3 avdd_dut avdd_dut avdd_dut r131 0 dnp c119 dnp vin_d vin_d r155 dnp r146 33 fb111 10 fb112 10 r147 33 r142 0 r148 1k r163 499 r144 1k dnp r151 0 dnp r145 1k dnp r43 0 dnp c125 2.2pf c126 dnp r159 dnp c124 dnp r143 0 fb110 10 cm4 cm4 1 2 34 5 6 ch_d ch_d c122 0.1 f c123 0.1 f a in p108 dnp r140 0 dnp r141 65 a in p107 channel d inh4 vga input connection t104 c128 0.1 f r150 1k r149 1k c127 dnp cm4 avdd_dut avdd_dut avdd_dut analog inputs 04418-041 vin_a vin_a r152 dnp r108 33 fb102 10 fb103 10 r110 33 r104 0 r103 0 fb101 10 r109 1k r160 499 r106 1k dnp r107 1k dnp r113 0 dnp c104 2.2pf r156 dnp c103 dnp cm1 cm1 1 2 34 5 6 ch_a ch_a c101 0.1 f c102 0.1 f a in p102 dnp r101 0 dnp r102 65 a in p101 channel a inh1 vga input connection t101 c107 0.1 f r112 1k r111 1k c106 dnp cm1 avdd_dut avdd_dut avdd_dut r105 0 dnp c105 dnp vin_b vin_b r153 dnp r121 33 fb105 10 fb106 10 r122 33 r117 0 r123 1k r161 499 r119 1k dnp r118 0 dnp r120 1k dnp r124 0 dnp c111 2.2pf c112 dnp r157 dnp c110 dnp r116 0 fb104 10 cm2 cm2 1 2 34 5 6 ch_b ch_b c108 0.1 f c109 0.1 f a in p104 dnp r114 0 dnp r115 65 a in p103 channel b inh2 vga input connection t102 c114 0.1 f r126 1k r125 1k c113 dnp cm2 avdd_dut avdd_dut avdd_dut dnp : do not populate figure 48. evaluation board schematic, dut analog inputs
ad9229 rev. a | page 27 of 40 1 2 3 4 6 8 5 7 9 10 11 12 drgnd drvdd dnc dtp agnd avdd avdd pdwn agnd vin +a vin ?a agnd gnd drvdd_dut gnd gnd avdd_dut avdd_dut dutclk gnd vin_d gnd 36 35 34 33 31 29 32 30 28 27 26 25 agnd drgnd drvdd lvdsbias agnd avdd avdd clk agnd vin +d vin ?d agnd 13 14 15 16 18 20 17 19 21 22 23 24 vin ?b vin +b agnd avdd vref reft sense refb avdd agnd vin +c vin ?c vin _b vin_b gnd avdd_dut vref_dut vsense_dut avdd_dut gnd vin _c vin_c 48 47 46 45 43 41 44 42 40 39 38 37 dco+ dco? fco+ fco? a?d d?b d+a d+b d+c d?c d+d d?d ad9229 vin_d gnd drvdd_dut avdd_dut avdd_dut avdd_dut gnd gnd vin_a gnd gnd r204 4.0k dco dco fco fco cha chb cha chb chc chc chd chd c203 0.1 f c202 10 f c201 0.1 f c204 0.1 f vin_a r203 10k pwdn enable jp201 avdd_dut jp202 r202 10k r228 10k r201 10k 1 2 3 digital test pattern enable pin 1 to pin 2 = 1010 1010 1010 pin 2 to pin 3 = 1000 0000 0000 optional clock oscillator avdd_vga avdd_dut avdd_dut jp204 jp203 1 4 2 3 eoh vcc gnd output cbelv3i66mt osc200 1 14 7 8 nc/enb vcc gnd output cx3600c-65 dnp osc201 c209 0.1 f c210 0.1 f c205 0.1 f r225 0 dnp r212 1k r211 1k r231 0 dnp r229 0 r230 0 dnp r214 22 r213 49.9 encode input p201 12 u202 avdd_dut:14 gnd:7 34 u202 avdd_dut:14 gnd:7 dutclk gndcd10 60 gndcd9 59 gndcd6 56 gndcd5 55 gndcd8 58 gndcd7 c10 c9 c6 c5 c8 d10 d9 d6 d5 d8 d7 c7 50 49 46 45 48 47 40 39 36 35 gndcd4 c4 d4 gndcd3 c3 d3 gndcd2 c2 d2 gndcd1 c1 d1 gndab10 a10 b10 gndab9 a9 b9 gndab8 a8 b8 gndab7 a7 b7 gndab6 a6 b6 gndab5 a5 b5 gndab4 a4 b4 gndab3 a3 b3 gndab2 a2 b2 gndab1 54 53 52 51 30 29 28 27 26 25 24 23 22 21 a1 b1 44 34 43 33 42 32 41 31 20 10 19 9 18 8 17 7 16 6 15 5 14 4 13 3 12 2 11 1 38 37 57 dco fco chc chd cha chb dco fco chc chd cha chb 1469169-1 r205-r210 optional output terminations r221 0 r222 0 r223 0 r224 0 avdd_dut avdd_dut vref_dut vsense_dut vref select vref = 1v = default r219 dnp c208 10 f c207 0.1 f r217 470k r218 0 dnp r215 2k r220 dnp r216 10k cw c206 0.1 f gnd adr510/adr520 1nv vout trim/nc u203 external reference circuit vref = 0.5v vref = external vref = 0.5v (1 + r219/r220) vref = 1v remove c208 when using external vref dnp : do not populate 04418-042 digital outputs p202 reference decoupling clock circuit reference circuit u201 r205 dnp r206 dnp r207 dnp r208 dnp r209 dnp r210 dnp figure 49. evaluation board schematic, dut, vr ef, clock inputs, and digital output interface
ad9229 rev. a | page 28 of 40 hilo pin hi gain range = 2.25v to 5.0v lo gain range = 0v to 1.0v ad8332 enbv enbl hilo vcm1 vin1 vip1 com1 lop1 25 26 27 28 29 30 31 32 lon1 vps1 inh1 lmd1 lmd2 inh2 vps2 lon2 1 2 3 4 5 6 7 8 rclmp gain mode vcm2 vin2 vip2 com2 lop2 16 15 14 13 12 11 10 9 comm voh1 vol1 vpsv nc vol2 voh2 comm 24 23 22 21 20 19 18 17 r304 187 r311 10k dnp r314 10k r315 274 c317 10 f c318 0.1 f c325 0.1 f c326 0.1 f c321 18nf r312 10 r307 187 r306 187 r309 187 r305 374 r308 374 r318 dnp r320 dnp r321 dnp c305 dnp c306 dnp r319 dnp c303 dnp c304 dnp l305 dnp l306 dnp l307 dnp l308 dnp l309 dnp l310 dnp l311 dnp l312 dnp c313 0.1 f c315 0.1 f c307 0.1 f c308 0.1 f c309 0.1 f c310 0.1 f ch_c ch_d ch_d ch_c c314 0.1 f avdd_vga avdd_vga avdd_vga r316 274 c322 18nf c323 22pf c324 22pf l313 120nh l314 120nh c327 0.1 f c328 0.1 f inh4 inh3 r311 10k dnp r317 10k dnp c320 10 f c319 0.1 f c316 0.1 f avdd_vga vg r310 100k dnp c312 0.1 f c311 1nf dnp : do not populate mode pin positive gain slope = 0v to 1.0v negative gain slope = 2.25v to 5.0v rclamp pin hilo pin = lo = 50mv hilo pin = hi = 75mv ext vg jp301 12 vg gnd avdd_vga r302 10k r303 39k cw vg external variable gain drive variable gain circuit (0v to 1.0v dc) optional vga drive circuit for channels c and d power-down enable (0v to 1v = disable power) 044181-003 u301 avdd_vga populate l305 to l312 with 0 resistors or design your own filter figure 50. evaluation board schematic, optional dut analog input drive
ad9229 rev. a | page 29 of 40 rclamp pin hilo pin = lo = 50mv hilo pin = hi = 75mv hilo pin hi gain range = 2.25v to 5.0v lo gain range = 0v to 1.0v ad8332 enbv enbl hilo vcm1 vin1 vip1 com1 lop1 25 26 27 28 29 30 31 32 lon1 vps1 inh1 lmd1 lmd2 inh2 vps2 lon2 1 2 3 4 5 6 7 8 rclmp gain mode vcm2 vin2 vip2 com2 lop2 16 15 14 13 12 11 10 9 comm voh1 vol1 vpsv nc vol2 voh2 comm 24 23 22 21 20 19 18 17 r403 187 r401 10k dnp r411 10k r412 274 c417 10 f c418 0.1 f c421 0.1 f c422 0.1 f c423 18nf r402 10k r406 187 r405 187 r408 187 r404 374 r407 374 r415 dnp r417 dnp r418 dnp c405 dnp c406 dnp r416 dnp c403 dnp c404 dnp l405 dnp l406 dnp l407 dnp l408 dnp l409 dnp l410 dnp l411 dnp l412 dnp c413 0.1 f c415 0.1 f c407 0.1 f c408 0.1 f c409 0.1 f c410 0.1 f ch_a ch_b ch_b ch_a c414 0.1 f avdd_vga avdd_vga avdd_vga r413 274 c424 18nf c425 22pf c426 22pf l413 120ph l414 120nh c427 0.1 f c428 0.1 f inh2 inh1 r409 10k dnp r414 10k dnp c420 10 f c419 0.1 f c416 0.1 f avdd_vga vg r409 100k dnp c412 0.1 f c411 1nf dnp : do not populate mode pin positive gain slope = 0v to 1.0v negative gain slope = 2.25v to 5.0v optional vga drive circuit for channels a and b populate l405 to l412 with 0 resistors or design your own filter power-down enable (0v to 1v = disable power) 044181-044 u401 figure 51. evaluation board schematic, optional dut analog input drive continued
ad9229 rev. a | page 30 of 40 power supply input 6v 2a max 04418-045 u502 c514 1 f c515 1 f 32 1 pwr_in 4 adp33339akc-5 output1 output4 input gnd vga_avdd l506 10 h u501 c502 1 f c503 1 f 32 1 pwr_in 4 adp33339akc-3 output1 output4 input gnd dut_avdd l504 10 h u503 c506 1 f c507 1 f 32 1 pwr_in 4 adp33339akc-3 output1 output4 input gnd dut_drvdd l505 10 h p503 c501 10 f 1 2 3 smdc110f f501 d501 s2a_rect 2a do-214aa d502 shot_rect 3a do-214ab 1 4 2 3 fer501 choke_coil r500 374 cr500 pwr_in optional power input c516 10 f c517 0.1 f avdd_vga 5.0v l503 10 h p1 p2 p3 p4 p5 p6 1 2 3 4 5 6 p501 dnp dut_avdd dut_drvdd vga_avdd c508 10 f c509 0.1 f avdd_dut 3.0v l502 10 h c504 10 f c505 0.1 f drvdd_dut 3.0v l501 10 h dnp : do not populate figure 52. evaluation board sc hematic, power supply inputs
ad9229 rev. a | page 31 of 40 04418-046 dnp : do not populate c621 0.1 f c619 0.1 f c620 0.1 f c627 0.1 f c630 0.1 f c631 0.1 f c613 0.1 f c614 0.1 f c617 0.1 f c618 0.1 f c632 0.1 f c625 0.1 f c628 0.1 f decoupling capacitors drvdd_dut avdd_vga avdd_dut h1 h2 h3 h4 mounting holes connected to ground 56 u202 avdd_dut : 14 gnd : 7 98 u202 avdd_dut : 14 gnd : 7 11 10 u202 avdd_dut : 14 gnd : 7 13 12 u202 avdd_dut : 14 gnd : 7 gnd unused gates figure 53. evaluation board schema tic, decoupling and miscellaneous
ad9229 rev. a | page 32 of 40 04418-047 figure 54. evaluation board layout, primary side
ad9229 rev. a | page 33 of 40 04418-048 figure 55. evaluation board layout, ground plane
ad9229 rev. a | page 34 of 40 04418-049 figure 56. evaluation board layout, power plane
ad9229 rev. a | page 35 of 40 04418-050 figure 57. evaluation board layout, secondary side (mirrored image)
ad9229 rev. a | page 36 of 40 table 11. evaluation board bill of materials (bom) item qnty. per board refdes device pkg. value mfg. mfg. part number 1 1 ad9229lfcsp_revc pcb pcb pcb 2 59 c327, c328, c630, c628, c629, c631, c632, c101, c102, c107, c108, c109, c114, c115, c116, c121, c122, c123, c128, c201, c203, c204, c205, c206, c207, c313, c314, c315, c312, c318, c319, c412, c316, c325,c326, c413, c414, c415, c418, c419, c416, c421, c422, c427, c428, c505, c509, c517, c613, c614, c617, c618, c619, c620, c621, c625, c209, c210, c627 capacitor 402 0.1 f, ceramic, x5r, 10 v, 10% tol panasonic ecj-0eb1a104k 3 4 c104, c111, c118, c125 capacitor 402 2.2 pf, ceramic, cog, 0.25 pf tol, 50 v murata grm1555c1h2r2gz01b 4 9 c202, c208, c317, c320, c417, c420, c504, c508, c516 capacitor 805 10 f, 6.3 v 10% ceramic x5r avx 08056d106kat2a 5 8 c307, c308, c309, c310, c407, c408, c409, c410 capacitor 603 0.1 f, ceramic, x7r, 16 v, 10% tol kemet c0603c104k4ractu 6 2 c311, c411 capacitor 402 1000 pf, ceramic, x7r, 25 v, 10% tol kemet c0402c102k3ractu 7 4 c321, c322, c423, c424 capacitor 402 0.018 f, ceramic, x7r, 16 v, 10% tol avx 0402yc183kat2a 8 4 c323, c324, c425, c426 capacitor 402 22 pf, ceramic, npo, 5% tol, 50 v kemet c0402c220j5gactu 9 1 c501 capacitor 1206 10 f, tantalum, 16 v, 10% tol kemet t491b106k016as 10 6 c502, c503, c506, c507, c514, c515 capacitor 603 1 f, ceramic, x5r, 6.3 v, 10% tol panasonic ecj-1vb0j105k 11 1 cr500 led 603 green, 4 v, 5 m candela panasonic lnj314g8tra 12 1 d502 diode do-214ab 3 a, 30 v, smc micro commercial co. sk33msct 13 1 d501 diode do-214aa 2 a, 50 v, smc micro commercial co. s2a 14 1 f501 fuse 1210 6.0 v, 2.2 a trip current resettable fuse tyco/raychem nanosmdc110f-2 15 1 fer501 ferrite bead 2020 10 h, 5 a, 50 v, 190 @ 100 mhz murata dlw5bsn191sq2l 16 12 fb101, fb102, fb103, fb104, fb105, fb106, fb107, fb108, fb109, fb110, fb111, fb112 ferrite bead 603 10 , test freq 100 mhz, 25% tol, 500 ma murata blm18ba100sn1 17 2 jp201, jp301 connector 2-pin 100 mil header jumper, 2-pin samtec tsw-102-07-g-s 18 3 jp204, jp203, jp202 connector 3-pin 100 mil header jumper, 3-pin samtec tsw-103-07-g-s
ad9229 rev. a | page 37 of 40 item qnty. per board refdes device pkg. value mfg. mfg. part number 19 6 l501, l502, l503, l504, l505, l506 ferrite bead 1210 10 h, bead core 3.2 2.5 1.6 smd, 2 a panasonic - ecg exc-cl3225u1 20 4 l313, l314, l413, l414 inductor 402 120 nh, test freq 100 mhz, 5% tol, 150 ma murata lqg15hnr12j02b 21 12 l305, l306, l307, l308, l309, l310, l405, l406, l407, l408, l409, l410, l311, l312, l411, l412 resistor 805 0 , 1/8 w, 5% tol panasonic erj-6gey0r00v 22 1 osc200 oscillator smt clock oscillator, 66.66 mhz, 3.3 v cts reeves cb3lv-3c-66m6666-t 23 5 p201, p101, p103, p105, p107 connector sma sidemount sma for 0.063" board thickness johnson components 142-0711-821 24 1 p202 connector header 1469169-1, right angle 2-pair, 25 mm, header assembly tyco 1469169-1 25 1 p503 connector 0.1", pcmt rapc722, power supply connector switchcraft sc1153 26 10 r201, r202, r228, r203, r312, r314, r317, r402, r411, r414 resistor 402 10 k, 1/16 w, 5% tol yageo america 9c04021a1002jlhf3 27 7 r225, r129, r142, r224 resistor 402 0 , 1/16 w, 5% tol yageo america 9c04021a0r00jlhf3 28 4 r102, r115, r128, r141 resistor 402 64.9 , 1/16 w, 1% tol panasonic erj-2rkf64r9x 29 4 r104, r116, r130, r143 resistor 603 0 , 1/10 w, 5% tol panasonic erj-3gey0r00v 30 14 r111, r112, r125, r126, r138, r139, r149, r150, r211, r212, r109, r123, r135, r148 resistor 402 1 k, 1/16 w, 1% tol panasonic erj-2rkf1001x 31 8 r108, r110, r121, r122, r134, r136, r146, r147 resistor 402 33 , 1/16 w, 5% tol yageo america 9c04021a33r0jlhf3 32 4 r160, r161, r162, r163 resistor 402 499 , 1/16 w, 1% tol panasonic erj-2rkf4990x 33 1 r215 resistor 402 2 k, 1/16 w, 5% tol yageo america 9c04021a2001jlhf3 34 1 r204 resistor 402 4.02 k, 1/16 w, 1% tol panasonic erj-2rkf4021x 35 1 r213 resistor 402 49.9 , 1/16 w, 0.5% tol susumu rr0510r-49r9-d 36 1 r214 resistor 402 22 , 1/16 w, 5% tol yageo america 9c04021a22r0jlhf3 37 2 r216,r302 potentiom eter 3-lead 10 k, cermet trimmer potentiometer, 18 turn top adjust, 10%, ? w bc components ct-94w-103 38 1 r217 resistor 402 470 k, 1/16 w, 5% tol yageo america 9c04021a4703jlhf3 39 1 r303 resistor 402 39 k, 1/16 w, 5% tol susumu rr0510p-393-d 40 8 r304, r306, r307, r309, r403, r405, r406, r408, resistor 402 187 , 1/16 w, 1% tol panasonic erj-2rkf1870x
ad9229 rev. a | page 38 of 40 item qnty. per board refdes device pkg. value mfg. mfg. part number 41 4 r305, r308, r404, r407, r500 resistor 402 374 , 1/16 w, 1% tol panasonic erj-2rkf3740x 42 4 r315, r316, r412, r413 resistor 402 274 , 1/16 w, 1% tol panasonic erj-2rkf2740x 43 4 t101, t102, t103, t104 transforme r cd542 adt1-1wt, 1:1 impedance ratio transformer mini-circuits adt1-1wt 44 2 u501, u503 ic sot-223 adp33339akc-3, 1.5 a, 3.0 v ldo regulator adi adp33339akc-3 45 2 u301, u401 ic lfcsp, cp- 32 ad8332acp, ultralow noise precision dual vga adi ad8332acp 46 1 u502 ic sot-223 adp33339akc-5 adi adp33339akc-5 47 1 u201 ic lfcsp, cp- 48-1 ad9229-65, quad 12-bit, 65 msps serial lvds 3 v adc adi ad9229bcpz-65 48 1 u203 ic sot-23 adr510ar, 1.0 v, precision low noise shunt voltage reference adi adr510ar 49 1 u202 ic tssop 74vhc04mtc, hex inverter fairchild 74vhc04mtc 50 4 mp101-104 part of assembly cbsb-14-01a-rt, 7/8" height, standoffs for circuit board support richco cbsb-14-01a-rt 51 4 mp105-108 part of assembly snt-100-bk-g-h, 100 mil jumpers samtec snt-100-bk-g-h 52 4 mp109-112 part of assembly 5-330808-3, pin sockets, closed end for osc200 amp 5-330808-3
ad9229 rev. a | page 39 of 40 outline dimensions pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 figure 58. 48-lead frame chip scale package [lfcsp] (cp-48-1) dimensions shown in millimeters ordering guide model temperature range package description package option ad9229bcpz-65 1 C40c to +85c 48-lead lfcsp cp-48-1 ad9229bcpzrl7-65 1 C40c to +85c 48-lead lfcsp cp-48-1 ad9229bcpz-50 1 C40c to +85c 48-lead lfcsp cp-48-1 AD9229BCPZRL7-50 1 C40c to +85c 48-lead lfcsp cp-48-1 ad9229-65eb evaluation board 1 z = pb-free part.
ad9229 rev. a | page 40 of 40 notes ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04418C0C9/05(a)

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